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Two-Stage RISC-V CPU

A two-stage pipelined RISC-V processor built in Logisim, connecting instruction fetch, execution, register files, and control logic.

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Simplified two-stage RISC-V processor diagram showing instruction fetch and execution.

A processor design project based on the CS61C CPU assignment. The implementation uses Logisim Evolution to build a two-stage pipeline: instruction fetch (IF) and execution (EX).

From instructions to circuits

The datapath connects the program counter and instruction memory to the register file, immediate generator, ALU, branch logic, and data memory. The controller translates instruction fields into the signals that coordinate these components.

The cover is a simplified architectural sketch. The complete circuit below shows the implementation and its test interfaces.

Full Logisim circuit for the two-stage RISC-V CPU, including the datapath and control logic.

Exploring the design

The repository includes the .circ circuit files, component diagrams, and a test harness. Open the circuits in Logisim Evolution to follow the datapath and inspect individual modules.

Tools: Logisim Evolution, RISC-V, and Python-based testing.